K7 Challenges Intel: 10/26/98

Tired of eating Intel’s performance dust, AMD is preparing a new entry in the battle for the CPU socket in high-end PCs. At the Microprocessor Forum earlier this month, chief architect Dirk Meyer described AMD’s nextgeneration K7 processor, on which the company will place its hopes for higher ASPs and improved profitability. The new processor was jointly developed by Meyer’s team in Austin (Texas) and Fred Weber’s team in Sunnyvale (Calif.). The K7’s three-issue superscalar design, which reorders instructions across a 72-instruction window, is the most aggressive of any x86 design yet announced. Despite this high degree of instruction-level parallelism (ILP), the K7’s 10-stage pipeline should allow it to achieve high clock rates. With silicon in hand, AMD is confident the processor will exceed 500 MHz in its first incarnation, which the company expects to deliver in the first half of 1999 (an industry euphemism for June). As Figure 1 shows, the new processor adopts the dualbus architecture of its competitor, Pentium II, and its ancestor, NexGen’s Nx686 (before it morphed into the Socket 7-based K6). The K7 employs large 64K L1 instruction and data caches, allowing it to function in low-cost systems without an L2, as well as in high-end systems with a backside L2. To avoid the multiprocessor and memory-bandwidth limitations of the K6’s Socket 7, the K7 adopts the Alpha 21264 bus. Although this bus is technically superior to Intel’s P6 bus, AMD may have bitten off more than it can chew, as it must create a new bus infrastructure without Intel’s help. AMD’s success in building a 100-MHz Socket 7 infrastructure for the K6, however, indicates that its goal is possible. Despite its 22-million-transistor complexity, the new processor is astonishingly small, occupying only 184 mm2 in AMD’s 0.25-micron process. In this mature process, AMD should experience none of the early yield and production K7 Challenges Intel New AMD Processor Could Beat Intel’s K